The present invention relates to a chip design, and more particularly, to a signal count reduction technique applied to a wafer-level package having multiple semiconductor dies assembled therein.
When a chip function of a target chip is achieved using a large-sized die, the fabrication of large-sized dies on a wafer will suffer from low yield and high cost. Given the same die area, the yield of one large die is lower than the yield of multiple small dies. More specifically, assuming that distribution of defects on a wafer is the same, a die yield of one large-sized die fabricated on the wafer is lower than a die yield of multiple small-sized dies which have the same area fabricated on the same wafer. However, splitting one large die into multiple smaller dies may bring some overhead. For example, a large number of signals will be introduced to achieve communications between different small-sized dies. As a result, an extra area will be needed by signal trace routing when more signals are needed to be transmitted between small-sized dies. Consequently, the production cost of using small-sized dies to implement the full function of a large-sized die is increased due to the extra area needed by signal traces routed between small-sized dies. Thus, there is a need for an innovative design which can achieve signal count reduction between dies.